http://www.jc-news.com/index.cgi
First off, there is a big of a confirmation that the K8 family, or at least one entry in it, will have the northbridge integrated onto the cpu die. I suspect that only the memory controller and not the rest of the north bridge is integrated as such.
* A new FAB30 design center stocked with 200 engineers will apparently have the sole purpose of creating chipsets for AMD's future platforms
* The south bridge for the K8 reportedly is being developed at this design center. According to this, the south bridge will support USB 2.0, HyperTransport, 5.1 sound, and DSL.
If you can think back to the end of last month, you may recall that I was informed that "AMD two weeks ago completed layout on an unannounced future south bridge design". As stated back then, the south bridge is allegedly very transistor heavy. This would gel perfectly with reports of only the memory controller being schtunked onto the K8 chip, as it would mean that all the excess features normally seen in the north bridge would have to appear in this AMD "south bridge".
* The post suggests that the south bridge is not too far forward in terms of development and advancement, but this makes sense unless you believe the silly rumours of the Hammers appearing early.
* 130nm test circuits are being run in Dresden. Hints here are that they are not progressing as optimally as would be hoped.
* And a little bit of info on the Athlons in Dresden (don't know whether it's talking about Thunderbirds or Palominos): 210 dice can fit on a 200mm diameter wafer, and yield (though this could mean anything from initial fab yield to after-packaging yield) is just above 70%.