原文

The following changes will be made:

* CPUID will change from 0F27h for C-1 step to 0F29h for D-1 step;
* Multiple VIDs are 1.475V, 1.5V, and 1.525V for up to 2.80GHz;
* Multiple VIDs are 1.475V, 1.5V, 1.525V and 1.55V for 3.06 GHz;
* Multiple VID will have one new s-spec and material master number per frequency;
* Electrical, mechanical, and thermal specification qualification required;
* Specifications stay the same and are within the designated FMB guidelines;
* Impedance pin functionality added (pin AE26) to support higher system bus (800MHz) platforms. No impact to existing platforms.