可以參考此篇文章(英文).
http://www.dfi-street.com/forum/showthread.php?t=11397

Row Cycle Time(tRC)

”This BIOS feature controls the memory module's Row Cycle Time or tRC. The row cycle time determines the minimum number of clock cycles a memory row takes to complete a full cycle, from row activation up to the precharging of the active row. Formula-wise, the row cycle time (tRC) = minimum row active time (tRAS) + row precharge time (tRP). Therefore, it is important to find out what the tRAS and tRP parameters are before setting the row cycle time. If the row cycle time is too long, it can reduce performance by unnecessarily delaying the activation of a new row after a completed cycle. Reducing the row cycle time allows a new cycle to begin earlier. However, if the row cycle time is too short, a new cycle may be initiated before the active row is sufficiently precharged. When this happens, there may be data loss or corruption. For optimal performance, use the lowest value you can, according to the tRC = tRAS + tRP formula. For example, if your memory module's tRAS is 7 clock cycles and its tRP is 4 clock cycles, then the row cycle time or tRC should be 11 clock cycles. However, if the row cycle time is too short, a new cycle may be initiated before the active row is sufficiently precharged. When this happens, there may be data loss or corruption.”

Large Influence on Bandwidth/Stability.

Suggested Settings for DFI: 7 yields the best performance, 15-17 yields the best stability/over clock. 22 is way overkill. Start at 16, and work your way down from there. 7 is usually much too tight for most average ram. Remember the tRC = tRAS + tRP formula. (Lower = Faster)

Idle Cycle Limit

Settings = Auto, 0-256 in varied increments.

From the DFI BIOS: “This BIOS setting specifies the number of memclocks before forcibly closing (pre-charging) an open page.” It appears that this setting is the maximum number of tries allowed for a page of memory to be read before arbitration kicks in and forces pre-charge once again for that page.

Slight Influence on Bandwidth/Larger Influence on Stability.

Suggested Settings for DFI: The Auto setting defaults to 256 clocks which seems to be overkill. If your RAM is lower grade----then I would stay with Auto. If your RAM is a step up, I would try 16-32 clocks. I had good luck with 16 clocks on BH-5. (Lower = Faster)

英文~看不懂,好心的陸行鳥大大幫忙解釋一下吧!!

感謝路行鳥大大，小弟英文太濫，金害= =

此項Bios調整設定，控制了記憶體模組的 Row Cycle Time (又稱tRC 。Cpu-Z顯示為
Bank Cycle Time (Trc) )
Trc 數值決定記憶體一個完整的循環週期時間
(從 row activation up to the precharging of the active row 為止)
公式就是:Trc=tRAS+tRP(RAS# precharge)
所以當tRAS與RP最小，您可以獲得最小的Trc值。





因此，要獲得Trc值，您需要先確定您的最小 tRAS與 tRP。
如果您設定的Trc值，比tRAS+tRP還小...記憶體在傳輸訊息時，
可能發生一個新的循環在記憶體重新充滿電之前開始，這將造成資訊喪失或是中斷。

又如果您設定的Trc值過大..則新的週期開始之前，將會有不需要的等待時間.....

以上..

Idle Cycle Limit的設定值從0~256。
此值決定了 "記憶體在強制關閉預先充電的分頁空間之前，記憶體所有的循環週期數目"

換句話說，該值決定

"在調停器中斷/強制重新預先充電該分頁之前，該記憶體分頁可以被讀取的次數"
此值對於記憶體頻寬影響甚小，對穩定性影響甚大。




DFI板子的Bios預設是256，則顯得有點過頭了..(除非您的DRAM真的不怎樣...)

原作者建議此值設定為AUTO。
假若您的DRAM系出名門，我們建議設定在16~32 循環週期之間。
在BH-5，原作者很幸運的設定 16。固此值越小，記憶體傳輸效率越快。

水大，這是您自己翻譯的嗎?小弟甘拜下風，我的tRAS(6)+tRP(3)=9，原來如此，感恩^^~

恩自己翻的....^^|||

所以如果有錯誤請大大不吝指正~^^

懂英文還是有用的,老外的東西終須老外的語言解釋~
嗯.......多謝水舞兄的教導!