作者cmwang

以下引自Socket 754的datasheet

2.4.2 Memory Controller
The processor’s memory controller provides a programmable interface to a variety of standard DDR SDRAM DIMM configurations. The following features are supported:
• Self-Refresh mode
• Unbuffered and registered DIMMs with a 64-bit data bus with optional 8 bits of Error Correcting Code (ECC) in one of the following two configurations:
— Up to three unbuffered DIMMs according to the loading described in the BIOS and Kernel Developer’s Guide for the AMD Athlon™ 64 and AMD Opteron™ Processors, order# 26094.
— Up to four registered DIMMs

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2.4.2.1.2 Registered DIMMs (Lidded Parts Only)
Registered DIMM support is provided on the desktop (lidde...