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Master Member
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引用:
Originally posted by IceOnly
假設我們有個k-stage的pipeline,每clock cycle time為T.
現在我們有n條指令(or task)
則時間應為k*T+(n-1)*T=(k+n-1)*T
而沒pipeline時間為n*k*T
因此速度增加的比率為n*k*T/(k+n-1)*T
對n取極限(->無限大),得出k,即理論上k條pipeline會比無pipeline快上k倍
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為什麼我要提這?
因為之前看某大大說prescott是因為stage多總和時間變長
效能才低落
有點和上面起衝突
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沒錯,這是理論上,管線越長時脈越快,處理速度也應該越快,但是還是牽涉到其他的問題
舉例來說,若是再"K-1"stage的地方出問題,就要重新來過,這要把之前已經在pipline裡的東西倒掉,空出整個單元給這個出錯的計算.
這個過程會嚴重的拖慢CPU的速度,所以管線越長,Branch prediction table就要越好越精確,以減少預測錯誤造成的延遲.
另外,管線越長,級數越多,最好就要保持管線時時都在"工作",才能展現長管線的高速處理優勢.
從Prescott的表現來看,Intel加強了分支預測來減少錯誤造成的延遲,並增加了L2快取來保持管線的"忙碌"
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