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Elite Member
您的住址: Cape Crozier
文章: 6,122
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小弟只看過 "皮"，所以只能告訴您一些找到的資料：
http://www.intel.com/technology/itj...1/pdf/art_4.pdf
引用:
1. C0—normal operation
2. C1—a low-power, low-latency state that assumes no support from chipset logic that retains all cached context
3. C2—a lower-power, slightly longer latency state than C1 that requires chipset support but still retains cached context
4. C3—a still lower power, longer latency state that also
requires chipset support but one in which the cached
context may be lost
Systems based on the IA-32 architecture will typically map the use of the HALT (HLT) instruction to the C1 state, the STOPCLOCK assertion to C2, and Deep Sleep (removal of the processor clock input signal) operation to the C3 state.
A documented sub-mode of the ACPI, C0 state is known as Clock Throttling (the thermal control functionality on the Pentium 4 processor would map to this sub-mode of the ACPI spec). In this mode, the operating system accesses logic to assert the STOPCLOCK signal with some predetermined duty cycle prior to the Pentium 4 processor, this logic had been resident in the chipset). The term "duty cycle" is used to refer to the characteristics of the signal applied by the chipset to the processor’s STOPCLOCK pin in order to reduce processor power dissipation.
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另外一篇，P.114 開始的 "Power State Definitions"：
http://www.hotchips.org/archive/hc1...df/02_gupta.pdf
如果沒記錯，各家 CPU 之 Spec. 應該都有對應的章節說明。對照他的圓圈圈圖 (雖然這樣說感覺很不專業) 與敘述應該可以有進一步瞭解吧~ |