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Golden Member
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http://www.mushkin.com/mushkin/pop-up/latencies.htm
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"Memory, in many ways is like a book, you can only read after opening a book to a certain page and paragraph within that particular page. The RAS Pulse Width is the time until a page can be closed again. Therefore, just by definition, the minimum tRAS must be the RAS-to-CAS delay plus the read latency (CAS delay). That is fine for FPM and EDO memory with their single word data transfers. With SDRAM, memory controllers started to output a chain of four consecutive quadwords on every access. With DDR, that number has increased to eight quadwords that effectively are two consecutive bursts of four.
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大意是說: 記憶體, 跟一本書一樣, 你要把書打開並翻到某頁才可以開始讀, RAS 就是在一個時間裡把那一頁給合起來. 所以, 最低tRAS 必須為 RAS to CAS delay 加 latency. 在EDO 跟 FPM記憶體上是沒問題的, 因為它們一次只傳送1 word data. 但在SDRAM裡, memory controller 一次傳送4個quadword. 在DDR裡變成8個quadword = 2組4個quadword
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Now imagine someone closes the book you are reading from in the middle of a sentence. Right in your face! And does it over and again. This is what happens if tRAS is set too short. So here is the really simple calculation: The second burst of four has at least to be initiated and prefetched into the output buffers (like you get a glimpse at the headline in a book) before you can close the page without losing all information. That means that the minimum tRAS would be tRCD+CAS latency + 2 cycles (to output the first burst of four and make way for the second burst in the output buffers).
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現在, 想像當你在閱讀一段文章時有人把你的書給合起來, 而且一直不斷的把你的書給合起來. 這就是tRAS 設太小的結果. 在你可以把書合起來並不會喪失資料前,第2組quadword 必須要被初始化和prefetch 到輸出 buffer 裡 (就像你先喵一下書裡的主題). 所以最低 tRAS 必須為 tRCD+CAS latency + 2 cycles (在輸出第一組quadword 時在output buffer 裡為下一組quadword 舖路)
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