PCDVD數位科技討論區 - 11/2/2/2 比 6/2/2/2 高?! (在FSB 200+ 時)

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11/2/2/2 比 6/2/2/2 高?!

從AMDMB上看到的

TheOtherDude 的測試結果:

100 MHz 2-2-2 (The varible is obviously tRAS)

2-782
3-782
4-782
5-782
6-782
7-816
8-799
9-799
10-799
11-799
12-799
13-782
14-767
15-782

133 MHz 2-2-2

2-1003
3-1003
4-1003
5-1003
6-1023
7-1065
8-1065
9-1043
10-1043
11-1043
12-1043
13-1023
14-1003
15-1003

150 MHz 2-2-2

2-1129
3-1129
4-1129
5-1129
6-1129
7-1151
8-1174
9-1174
10-1174
11-1174
12-1174
13-1151
14-1129
15-1129

166 MHz 2-2-2

2-1254
3-1254
4-1254
5-1254
6-1254
7-1279
8-1304
9-1304
10-1304
11-1304
12-1304
13-1279
14-1254
15-1254

200 MHz 2-2-2

2-1478
3-1478
4-1478
5-1478
6-1478
7-1505
8-1535
9-1535
10-1565
11-1565
12-1565
13-1535
14-1505
15-1505

回覆: 11/2/2/2 比 6/2/2/2 高?! (在FSB 200+ 時)

引用:

Originally posted by HardCorr

從AMDMB上看到的

誤差值吧
差不了多少...

回覆: 11/2/2/2 比 6/2/2/2 高?!

引用:

Originally posted by HardCorr

從AMDMB上看到的

推~~
希望有大大來解釋一下
這好像跟之前看記體設定的說法不同

我覺得是軟體的Bug所造成...

http://www.mushkin.com/mushkin/pop-up/latencies.htm

引用:

"Memory, in many ways is like a book, you can only read after opening a book to a certain page and paragraph within that particular page. The RAS Pulse Width is the time until a page can be closed again. Therefore, just by definition, the minimum tRAS must be the RAS-to-CAS delay plus the read latency (CAS delay). That is fine for FPM and EDO memory with their single word data transfers. With SDRAM, memory controllers started to output a chain of four consecutive quadwords on every access. With DDR, that number has increased to eight quadwords that effectively are two consecutive bursts of four.

大意是說: 記憶體, 跟一本書一樣, 你要把書打開並翻到某頁才可以開始讀, RAS 就是在一個時間裡把那一頁給合起來. 所以, 最低tRAS 必須為 RAS to CAS delay 加 latency. 在EDO 跟 FPM記憶體上是沒問題的, 因為它們一次只傳送1 word data. 但在SDRAM裡, memory controller 一次傳送4個quadword. 在DDR裡變成8個quadword = 2組4個quadword

引用:

Now imagine someone closes the book you are reading from in the middle of a sentence. Right in your face! And does it over and again. This is what happens if tRAS is set too short. So here is the really simple calculation: The second burst of four has at least to be initiated and prefetched into the output buffers (like you get a glimpse at the headline in a book) before you can close the page without losing all information. That means that the minimum tRAS would be tRCD+CAS latency + 2 cycles (to output the first burst of four and make way for the second burst in the output buffers).

現在, 想像當你在閱讀一段文章時有人把你的書給合起來, 而且一直不斷的把你的書給合起來. 這就是tRAS 設太小的結果. 在你可以把書合起來並不會喪失資料前,第2組quadword 必須要被初始化和prefetch 到輸出 buffer 裡 (就像你先喵一下書裡的主題). 所以最低 tRAS 必須為 tRCD+CAS latency + 2 cycles (在輸出第一組quadword 時在output buffer 裡為下一組quadword 舖路)

引用:

Originally posted by HardCorr
http://www.mushkin.com/mushkin/pop-up/latencies.htm

大意是說: 記憶體, 跟一本書一樣, 你要把書打開並翻到某頁才可以開始讀, RAS 就是在一個時間裡把那一頁給合起來. 所以, 最低tRAS 必須為 RAS to CAS delay 加 latency. 在EDO 跟 FPM記憶體上是沒問題的, 因為它們一次只傳送1 word data. 但在SDRAM裡, memory controller 一次傳送4個quadword. 在DDR裡變成8個quadword = 2組4個quadword

現在, 想像當你在閱讀一段文章時有人把你的書給合起來, 而且一直不斷的把你的書給合起來. 這就是tRAS 設太小的結果. 在你可以把書合起來並不會喪失資料前,第2組quadword 必須要被初始化和prefetch 到輸出 buffer 裡 (就像你先喵一下書裡的主題). 所以最低 tRAS 必須為 tRCD+CAS latency + 2 cycles (在輸出第一組quadword 時在output buffer 裡為下一組quadword 舖路)

這麼說來2-2-2-11才是DDR400下的最佳化了？！
小弟趕緊來測測..

受教了:like:
可是找不到11時又該設多少?

是有聽過這個說法!
感謝!:D

謝謝你的分享資訊，馬上來修改試試，因為我一直用5.2.2.2。

好神奇
等會試看看