非OPTERON 940的CPU,
理論上是不能搭配ECC+REG

h7878220兄台的例子可以算是特例,運氣真不錯!

3000+配上K8NXP-9也是可以跑

DDR266........ :laugh: 哇勒 ~ 請問大大有關cnq嗎 :rolleyes:

買了兩條創見 ECC回家 用MEMTEST86下去看 ECC還是OFF

拿到EVEREST下面 從晶片組選項下去看

到底ECC有沒有打開啊 :stupefy: :confused:

看起來是沒有啟動ECC , 也許要手動在BIOS下開啟吧 , 我猜的 !

以下引自Socket 754的datasheet

2.4.2 Memory Controller
The processor’s memory controller provides a programmable interface to a variety of standard DDR SDRAM DIMM configurations. The following features are supported:
• Self-Refresh mode
• Unbuffered and registered DIMMs with a 64-bit data bus with optional 8 bits of Error Correcting Code (ECC) in one of the following two configurations:
— Up to three unbuffered DIMMs according to the loading described in the BIOS and Kernel Developer’s Guide for the AMD Athlon™ 64 and AMD Opteron™ Processors, order# 26094.
— Up to four registered DIMMs

snipped...

2.4.2.1.2 Registered DIMMs (Lidded Parts Only)
Registered DIMM support is provided on the desktop (lidded) parts only. The following list summarizes the differences in the pin interface between registered and unbuffered DIMMs:
• The MEMRESET_L pin is required only for registered DIMMs and is used to reset the register as required to support the Suspend-to-RAM power management state (ACPI S3).
• Registered DIMMS present less loading than unbuffered DIMMs. Therefore, the processor’s memory controller supports up to four registered DIMMs or up to three unbuffered DIMMs. Refer to the BIOS and Kernel Developer’s Guide for the AMD Athlon™ 64 and AMD Opteron™ Processors, order# 26094, for restrictions on support for three unbuffered DIMMs.
• A fully populated registered DIMM configuration requires only four differential clock pairs
• Registered DIMMs configured with x4 DRAMs require an additional eight DQS pins without ECC support or nine DQS pins with ECC support. The processor’s memory controller provides a
total of 18 DQS pins to accommodate this requirement. The additional DQS pins can be connected to the DIMMs’ Data Mask (DM) pins when connected to x8 or x16 DIMMs. DIMMs populated
with x4 devices normally connect the DRAM’s Data Mask (DM) pins to VSS. The DM pins are used for partial write support when connected to x8 or x16 devices.
• Registered DIMMs typically connect only to the ‘A’ copy of the memory address and command signals.

snipped....

鵝前一陣子就借舊server上的512MB PC2100 ECC/registered RAM給S754的SP2500用,實際上是可以work的,只是比DDR400還慢就是了,連SP2500都可以吃ECC/registered RAM了,沒道理其它K8(無蓋者如DTR/Mobile版除外)不行吧:p:p....

成功開啟的大大可以把圖貼上來嗎 :confused:

我記的BIOS裡有選項要開啟

大大知到K8NS Ultra 939 要怎麼打開嗎 :rolleyes:

記得進BIOS之後要先按Alt+F1開啟技嘉隱藏選項
到調整記憶體延遲的選單裡就可以看到ECC了